This invention relates, in general, to semiconductor wafer processing, and more particularly to methods for forming power metal oxide semiconductor field effect transistor (MOSFET) devices.
Power MOSFET devices are well known and are used in many applications including automotive electronics, portable electronics, power supplies, and telecommunications. One important electrical characteristic of a power MOSFET device is its on-state resistance (R.sub.DS(on)), which is defined as the total resistance encountered by a drain current as it flows from the drain terminal to the source terminal. In a vertical power MOSFET device, this total resistance is composed of several resistive components commonly referred to as an inversion channel resistance, a gate-drain accumulation resistance, a junction field effect transistor (JFET) pinch region resistance (i.e., a JFET resistance), a spreading resistance, a bulk resistance, and a starting substrate resistance.
In order to allow manufacturers to produce power MOSFET devices having higher current carrying capability in smaller packages, it would be advantageous to have MOSFET structures that reduce one or more of the above resistive components thereby lowering R.sub.DS(on). It would be of further advantage to do so without detrimentally impacting other MOSFET characteristics.